Tender Description:
DESIGN DEVELOPMENT AND PRODUCTION OF CONTROL MODULE (CPU), EP SIGNAL CONDITIONING MODULE-9 CHANNEL, CG SIGNAL CONDITIONING MODULE-7 CHANNEL, TWO CHANNEL BREAK CAPACITOR MODULE AND TEST JACK MONITORING MODULE AS PER ANNEUXRE-T1 TO ECIL HYDERABAD
Dates:
Published on
June 29, 2024, 10:24 p.m.
Bid Opening Date
July 20, 2024, 2:30 p.m.
Doc Download started
June 29, 2024, 10:24 p.m.
Doc Download ended
July 19, 2024, 9:30 p.m.